Reconfigurable Hardware Accelerator of Morphological Image Processor

Ming Yi Lin, Sheng Hsien Hsieh, Ching Han Chen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

1 引文 斯高帕斯(Scopus)

摘要

Researchers emphasize the importance of hardware accelerators for mathematical morphology. If there are any issues, the hardware architecture may need to be redesigned. Thus, we propose a novel, reconfigurable hardware architecture with pipeline techniques for acceleration. With the order control register, there is no need to modify the architecture even if different results are expected. Furthermore, the hardware architecture caters to specific purposes instead of requiring a purpose-built hardware design.

原文???core.languages.en_GB???
主出版物標題2023 IEEE 3rd International Conference on Electronic Communications, Internet of Things and Big Data, ICEIB 2023
編輯Teen-Hang Meen
發行者Institute of Electrical and Electronics Engineers Inc.
頁面348-351
頁數4
ISBN(電子)9798350333862
DOIs
出版狀態已出版 - 2023
事件3rd IEEE International Conference on Electronic Communications, Internet of Things and Big Data, ICEIB 2023 - Taichung, Taiwan
持續時間: 14 4月 202316 4月 2023

出版系列

名字2023 IEEE 3rd International Conference on Electronic Communications, Internet of Things and Big Data, ICEIB 2023

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???event.eventtypes.event.conference???3rd IEEE International Conference on Electronic Communications, Internet of Things and Big Data, ICEIB 2023
國家/地區Taiwan
城市Taichung
期間14/04/2316/04/23

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