TY - JOUR
T1 - Rapid Fabrication of 100 nm or Thinner Fully Depleted Silicon-on-Insulator Materials for Ultralow Energy Consumption
AU - Lee, Benjamin T.H.
AU - Huang, Ching Han
AU - Ho, Chia Che
AU - Lo, Fa Sain
N1 - Publisher Copyright:
Copyright © 2018 American Chemical Society.
PY - 2018/5/25
Y1 - 2018/5/25
N2 - The fully depleted silicon-on-insulator (FD-SOI) wafer is the core material of the FD-SOI technology used for manufacturing the applications with ultralow energy consumption for internet of things, artificial intelligence, automotive, and wearable devices. Ion-cut process is the main technology to fabricate FD-SOI wafers. After ion cutting, the silicon layer transferred on the insulator includes a spongelike damaged layer. Therefore, it must contain a thinning buffer layer with a thickness more than 150 nm to remove the damaged layer by a polishing step. The requirement of the additional buffer layer makes the direct fabrication of a less than 100 nm thick SOI layer from the as-split status impossible. Here, we develop a process based on solid-phase epitaxial growth (SPEG) technique, abandoning the polishing step, and thus achieve a one-step fabrication of FD-SOI substrate. First, inducing amorphization of an SOI layer via blistering supersaturated hydrogen ions through microwaving fully consumes the possible stable defect clusters. Next, using SPEG technique catalyzed by surrounding hydrogen ions restores the amorphized SOI layer to the initial crystalline structure. To approach the purpose, a silicon (Si)-clad layer deposited on the oxidized surface was used. The Si-clad layer has two functions promoting the success of SPEG processing. It acts as a filter to prevent co-implanted impurities in the silicon layer to avoid the occurrence of crystal segregation during recrystallization. It also serves as a sacrificial layer to bring the split location close to the implant peak causing the hydrogen concentration in the entire SOI layer in supersaturation. When amorphizing this layer, an undamaged crystalline layer is retained at the interface of the SiO2/Si as a seed layer to promote the regrowth of a perfect SOI layer in a argon-annealing step. By integrating with the ion-shower implantation used in flat-panel display manufacturing, the technology can fabricate the next generation of larger SOI wafers without the need to upgrade the ion implanter.
AB - The fully depleted silicon-on-insulator (FD-SOI) wafer is the core material of the FD-SOI technology used for manufacturing the applications with ultralow energy consumption for internet of things, artificial intelligence, automotive, and wearable devices. Ion-cut process is the main technology to fabricate FD-SOI wafers. After ion cutting, the silicon layer transferred on the insulator includes a spongelike damaged layer. Therefore, it must contain a thinning buffer layer with a thickness more than 150 nm to remove the damaged layer by a polishing step. The requirement of the additional buffer layer makes the direct fabrication of a less than 100 nm thick SOI layer from the as-split status impossible. Here, we develop a process based on solid-phase epitaxial growth (SPEG) technique, abandoning the polishing step, and thus achieve a one-step fabrication of FD-SOI substrate. First, inducing amorphization of an SOI layer via blistering supersaturated hydrogen ions through microwaving fully consumes the possible stable defect clusters. Next, using SPEG technique catalyzed by surrounding hydrogen ions restores the amorphized SOI layer to the initial crystalline structure. To approach the purpose, a silicon (Si)-clad layer deposited on the oxidized surface was used. The Si-clad layer has two functions promoting the success of SPEG processing. It acts as a filter to prevent co-implanted impurities in the silicon layer to avoid the occurrence of crystal segregation during recrystallization. It also serves as a sacrificial layer to bring the split location close to the implant peak causing the hydrogen concentration in the entire SOI layer in supersaturation. When amorphizing this layer, an undamaged crystalline layer is retained at the interface of the SiO2/Si as a seed layer to promote the regrowth of a perfect SOI layer in a argon-annealing step. By integrating with the ion-shower implantation used in flat-panel display manufacturing, the technology can fabricate the next generation of larger SOI wafers without the need to upgrade the ion implanter.
KW - FD-SOI
KW - hydrogen enhancement
KW - ion-cut process
KW - layer transfer
KW - solid-phase epitaxial-growth process
KW - ultralow energy consumption
UR - http://www.scopus.com/inward/record.url?scp=85078375001&partnerID=8YFLogxK
U2 - 10.1021/acsanm.8b00602
DO - 10.1021/acsanm.8b00602
M3 - 期刊論文
AN - SCOPUS:85078375001
SN - 2574-0970
VL - 1
SP - 2414
EP - 2420
JO - ACS Applied Nano Materials
JF - ACS Applied Nano Materials
IS - 5
ER -