Rapid Fabrication of 100 nm or Thinner Fully Depleted Silicon-on-Insulator Materials for Ultralow Energy Consumption

Benjamin T.H. Lee, Ching Han Huang, Chia Che Ho, Fa Sain Lo

研究成果: 雜誌貢獻期刊論文同行評審

2 引文 斯高帕斯(Scopus)


The fully depleted silicon-on-insulator (FD-SOI) wafer is the core material of the FD-SOI technology used for manufacturing the applications with ultralow energy consumption for internet of things, artificial intelligence, automotive, and wearable devices. Ion-cut process is the main technology to fabricate FD-SOI wafers. After ion cutting, the silicon layer transferred on the insulator includes a spongelike damaged layer. Therefore, it must contain a thinning buffer layer with a thickness more than 150 nm to remove the damaged layer by a polishing step. The requirement of the additional buffer layer makes the direct fabrication of a less than 100 nm thick SOI layer from the as-split status impossible. Here, we develop a process based on solid-phase epitaxial growth (SPEG) technique, abandoning the polishing step, and thus achieve a one-step fabrication of FD-SOI substrate. First, inducing amorphization of an SOI layer via blistering supersaturated hydrogen ions through microwaving fully consumes the possible stable defect clusters. Next, using SPEG technique catalyzed by surrounding hydrogen ions restores the amorphized SOI layer to the initial crystalline structure. To approach the purpose, a silicon (Si)-clad layer deposited on the oxidized surface was used. The Si-clad layer has two functions promoting the success of SPEG processing. It acts as a filter to prevent co-implanted impurities in the silicon layer to avoid the occurrence of crystal segregation during recrystallization. It also serves as a sacrificial layer to bring the split location close to the implant peak causing the hydrogen concentration in the entire SOI layer in supersaturation. When amorphizing this layer, an undamaged crystalline layer is retained at the interface of the SiO2/Si as a seed layer to promote the regrowth of a perfect SOI layer in a argon-annealing step. By integrating with the ion-shower implantation used in flat-panel display manufacturing, the technology can fabricate the next generation of larger SOI wafers without the need to upgrade the ion implanter.

頁(從 - 到)2414-2420
期刊ACS Applied Nano Materials
出版狀態已出版 - 25 5月 2018


深入研究「Rapid Fabrication of 100 nm or Thinner Fully Depleted Silicon-on-Insulator Materials for Ultralow Energy Consumption」主題。共同形成了獨特的指紋。