Q-learning based dynamic voltage scaling for designs with graceful degradation

Yu Guang Chen, Wan Yu Wen, Tao Wang, Yiyu Shi, Shih Chieh Chang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

4 引文 斯高帕斯(Scopus)

摘要

Dynamic voltage scaling (DVS) has been widely used to suppress power consumption in modern designs. The decision of optimal operating voltage at runtime should consider the variations in workload, process as well as environment. As these variations are hard to predict accurately at design time, various reinforcement learning based DVS schemes have been proposed in the literature. However, none of them can be readily applied to designs with graceful degradation, where timing errors are allowed with bounded probability to trade for further power reduction. In this paper, we propose a Q-learning based DVS scheme dedicated to the designs with graceful degradation. We compare it with two deterministic DVS schemes, i.e., a stepping based scheme and a statistical modeling based scheme. Experimental results on three 45nm industrial designs show that the proposed Q-learning based scheme can achieve up to 83.9% and 29.1% power reduction respectively with 0.01 timing error probability bound. To the best of the authors' knowledge, this is the first in-depth work to explore reinforcement learning based DVS schemes for designs with graceful degradation.

原文???core.languages.en_GB???
主出版物標題ISPD 2015 - Proceedings of the ACM International Symposium on Physical Design 2015
發行者Association for Computing Machinery
頁面41-48
頁數8
ISBN(電子)9781450333993
DOIs
出版狀態已出版 - 29 3月 2015
事件18th ACM International Symposium on Physical Design, ISPD 2015 - Monterey, United States
持續時間: 29 3月 20151 4月 2015

出版系列

名字Proceedings of the International Symposium on Physical Design
29-March-2015

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???event.eventtypes.event.conference???18th ACM International Symposium on Physical Design, ISPD 2015
國家/地區United States
城市Monterey
期間29/03/151/04/15

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