Post-bond test techniques for TSVs with crosstalk faults in 3D ICs

Yu Jen Huang; Jin Fu Li; Che Wei Chou

doi:10.1109/VLSI-DAT.2012.6212658

Post-bond test techniques for TSVs with crosstalk faults in 3D ICs

Yu Jen Huang, Jin Fu Li, Che Wei Chou

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

18 引文斯高帕斯（Scopus）

摘要

Three-dimensional (3D) integration is expected to cope with the difficulties faced by current 2D system-on-chip designs using through silicon via (TSV). However, coupling capacitance exists between two neighboring TSVs such that TSVs are prone to crosstalk faults. In this paper, we propose a builtin self-test (BIST) scheme for the post-bond test of TSVs with crosstalk faults in 3D ICs. A test algorithm for testing crosstalk faults of TSVs is proposed. The proposed BIST scheme has the feature of low area cost. Simulation results show that the area overhead of the BIST circuit implemented with 90nm CMOS technology for a 51216 TSV array in which each TSV cell size is 15 15m ² is 6.7%.

原文	???core.languages.en_GB???
主出版物標題	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VLSI-DAT.2012.6212658
出版狀態	已出版 - 2012
事件	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan 持續時間: 23 4月 2012 → 25 4月 2012

出版系列

名字	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
國家/地區	Taiwan
城市	Hsinchu
期間	23/04/12 → 25/04/12

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10.1109/VLSI-DAT.2012.6212658

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Huang, Y. J., Li, J. F., & Chou, C. W. (2012). Post-bond test techniques for TSVs with crosstalk faults in 3D ICs. 於 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers [6212658] (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212658

@inproceedings{4aac3548f96e497fb67ace9020dc5ee3,

title = "Post-bond test techniques for TSVs with crosstalk faults in 3D ICs",

abstract = "Three-dimensional (3D) integration is expected to cope with the difficulties faced by current 2D system-on-chip designs using through silicon via (TSV). However, coupling capacitance exists between two neighboring TSVs such that TSVs are prone to crosstalk faults. In this paper, we propose a builtin self-test (BIST) scheme for the post-bond test of TSVs with crosstalk faults in 3D ICs. A test algorithm for testing crosstalk faults of TSVs is proposed. The proposed BIST scheme has the feature of low area cost. Simulation results show that the area overhead of the BIST circuit implemented with 90nm CMOS technology for a 51216 TSV array in which each TSV cell size is 15 15m 2 is 6.7%.",

author = "Huang, {Yu Jen} and Li, {Jin Fu} and Chou, {Che Wei}",

year = "2012",

doi = "10.1109/VLSI-DAT.2012.6212658",

language = "???core.languages.en_GB???",

isbn = "9781457720819",

series = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

booktitle = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

note = "null ; Conference date: 23-04-2012 Through 25-04-2012",

}

Huang, YJ, Li, JF & Chou, CW 2012, Post-bond test techniques for TSVs with crosstalk faults in 3D ICs. 於 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212658, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, 23/04/12. https://doi.org/10.1109/VLSI-DAT.2012.6212658

Post-bond test techniques for TSVs with crosstalk faults in 3D ICs. / Huang, Yu Jen; Li, Jin Fu; Chou, Che Wei.

2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212658 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

TY - GEN

T1 - Post-bond test techniques for TSVs with crosstalk faults in 3D ICs

AU - Huang, Yu Jen

AU - Li, Jin Fu

AU - Chou, Che Wei

PY - 2012

Y1 - 2012

N2 - Three-dimensional (3D) integration is expected to cope with the difficulties faced by current 2D system-on-chip designs using through silicon via (TSV). However, coupling capacitance exists between two neighboring TSVs such that TSVs are prone to crosstalk faults. In this paper, we propose a builtin self-test (BIST) scheme for the post-bond test of TSVs with crosstalk faults in 3D ICs. A test algorithm for testing crosstalk faults of TSVs is proposed. The proposed BIST scheme has the feature of low area cost. Simulation results show that the area overhead of the BIST circuit implemented with 90nm CMOS technology for a 51216 TSV array in which each TSV cell size is 15 15m 2 is 6.7%.

AB - Three-dimensional (3D) integration is expected to cope with the difficulties faced by current 2D system-on-chip designs using through silicon via (TSV). However, coupling capacitance exists between two neighboring TSVs such that TSVs are prone to crosstalk faults. In this paper, we propose a builtin self-test (BIST) scheme for the post-bond test of TSVs with crosstalk faults in 3D ICs. A test algorithm for testing crosstalk faults of TSVs is proposed. The proposed BIST scheme has the feature of low area cost. Simulation results show that the area overhead of the BIST circuit implemented with 90nm CMOS technology for a 51216 TSV array in which each TSV cell size is 15 15m 2 is 6.7%.

UR - http://www.scopus.com/inward/record.url?scp=84864037022&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2012.6212658

DO - 10.1109/VLSI-DAT.2012.6212658

M3 - 會議論文篇章

AN - SCOPUS:84864037022

SN - 9781457720819

T3 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

BT - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Y2 - 23 April 2012 through 25 April 2012

ER -

Huang YJ, Li JF, Chou CW. Post-bond test techniques for TSVs with crosstalk faults in 3D ICs. 於 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212658. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). doi: 10.1109/VLSI-DAT.2012.6212658

Post-bond test techniques for TSVs with crosstalk faults in 3D ICs

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