PLL circuits

Muh Tian Shiue, Chorng Kuang Wang

研究成果: 書貢獻/報告類型篇章同行評審


Phase-locked loop (PLL) is a circuit architecture that causes a particular system to track with another one. More precisely, PLL synchronizes a signal (usually a local oscillator output) with a reference or an input signal in frequency as well as in phase. Phase locking is a useful technique that can provide effective synchronization solutions in many data transmission systems such as optical communications, telecommunications, disk drive systems, and local networks, inwhich data are transmitted in baseband or passband. In general, only data signals are transmitted in most of these applications, namely, clock signals are not transmitted in order to save hardware cost. Therefore, the receiver should have somemechanisms to extract the clock information from the received data stream in order to recover the transmitted data. The scheme is called a timing recovery or clock recovery. The cost of electronic interfaces in communication systems raises as the data rate gets higher. Hence, high-speed circuits are the critical issue of the high data rate systems implementation, and the advanced very large scale integration (VLSI) technology plays an important role in cost reduction for the highspeed communication systems.

主出版物標題Analog and VLSI Circuits
發行者CRC Press
ISBN(列印)1420058916, 9781420058918
出版狀態已出版 - 1 1月 2009


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