Partial reset and scan for flip-flops based on states requirement for test generation

H. Ch Liang, Ch L. Lee, J. E. Chen

研究成果: 會議貢獻類型會議論文同行評審

6 引文 斯高帕斯(Scopus)

摘要

This paper proposes a method to select flip-flops for partial reset and/or partial scan for sequential circuits to increase their testability. The method gives weights for flip-flops for consideration for partial reset and/or scan based on information on required states for activating faults and the number of faults which propagate to flip-flops, which are obtained during test generation. Since the above information offers the reasons causing the untestable and/or hard-to-detect faults, the method is very efficient in locating flip-flops for partial reset and/or scan to ease test generation task. Experiments showed that this method selected less number of flip-flops for partial reset and scan while produced more testable circuits for benchmark circuits.

原文???core.languages.en_GB???
頁面341-346
頁數6
出版狀態已出版 - 1998
事件Proceedings of the 1998 16th IEEE VLSI Test Symposium - Monterey, CA, USA
持續時間: 26 4月 199830 4月 1998

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???event.eventtypes.event.conference???Proceedings of the 1998 16th IEEE VLSI Test Symposium
城市Monterey, CA, USA
期間26/04/9830/04/98

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