Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMs

Spin-transfer-torque magnetic random access memory (STT-MRAM) is a candidate for next-generation memory to cope with scaling challenges of conventional memories. However, the STT-MRAM has a small on/off resistance ratio which poses challenges in designing the reference resistance. An effective approach to cope with this issue is to design a trimmable reference resistance that allows post-production control of the reference resistance. A trimming test should be used in the production test to find an appropriate reference resistance. In this paper, a parallel-check trimming test (PCTT) approach aimed at significantly reducing the trimming test time is proposed. In comparison with the existing binary-judge-based search test approach, the proposed PCTT approach drastically reduces trimming test time with nearly the same read yield.