OPAM: An efficient output phase assignment for multilevel logic minimization

Chin Long Wey; Sin Min Chang; Jing Yang Jou

OPAM: An efficient output phase assignment for multilevel logic minimization

Chin Long Wey, Sin Min Chang, Jing Yang Jou

電機工程學系

研究成果: 會議貢獻類型 › 會議論文 › 同行評審

摘要

When a multiple-output function (z₁, z₂,...,z_m) of multilevel logic is realized by complex gates, the option often exists to realize either z_i or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system).

原文	???core.languages.en_GB???
頁面	270-273
頁數	4
出版狀態	已出版 - 1989
事件	Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA 持續時間: 2 10月 1989 → 4 10月 1989

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors
城市	Cambridge, MA, USA
期間	2/10/89 → 4/10/89

引用此

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abstract = "When a multiple-output function (z1, z2,...,zm) of multilevel logic is realized by complex gates, the option often exists to realize either zi or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system).",

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T2 - Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors

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AU - Chang, Sin Min

AU - Jou, Jing Yang

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N2 - When a multiple-output function (z1, z2,...,zm) of multilevel logic is realized by complex gates, the option often exists to realize either zi or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system).

AB - When a multiple-output function (z1, z2,...,zm) of multilevel logic is realized by complex gates, the option often exists to realize either zi or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system).

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M3 - 會議論文

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Y2 - 2 October 1989 through 4 October 1989

ER -

OPAM: An efficient output phase assignment for multilevel logic minimization

摘要

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引用此