ON THE CONSTRUCTION OF A PROLOG‐BASED VERIFIER FOR SYSTOLIC ARRAY DESIGNS

Mathematics

• Systolic Array 100%
• Architecture 45%
• Design 43%
• Prolog 37%
• Formal Specification 21%
• Formal Verification 20%
• Specification Languages 19%
• Mathematical Induction 19%
• LU decomposition 19%
• Backtracking 17%
• Pattern Matching 17%
• Formal Proof 17%
• Locality 16%
• Matrix multiplication 16%
• Rewriting 15%
• Symbolic Computation 15%
• Proof by induction 13%
• Reasoning 13%
• Specification 12%
• Verify 11%
• Strategy 9%
• Regularity 9%
• Standards 7%

Engineering & Materials Science

• Systolic arrays 89%
• UNIX 17%
• Formal specification 16%
• Formal verification 16%
• Specification languages 15%
• Pattern matching 15%
• Decomposition 10%
• Specifications 8%