ON THE CONSTRUCTION OF A PROLOG‐BASED VERIFIER FOR SYSTOLIC ARRAY DESIGNS

Keyphrases

• Array Design 100%
• Verifier 100%
• Systolic Array 100%
• Systolic Architecture 75%
• Prolog 50%
• System Call 25%
• Formal Specification 25%
• Formal Verification 25%
• Symbolic Computation 25%
• Proof Techniques 25%
• LU Decomposition 25%
• Operational Rules 25%
• Formal Proof 25%
• Systolic Design 25%
• Formal Description 25%
• Pattern Matching 25%
• Formal Reasoning 25%
• Specification Language 25%
• Matrix multiplication 25%
• Mathematical Induction 25%
• Induction Techniques 25%

Computer Science

• Systolic Arrays 100%
• System Calls 16%
• Formal Specification 16%
• Backtracking 16%
• Matrix Multiplication 16%
• Proof Technique 16%
• Formal Description 16%
• Pattern Matching 16%
• Specification Language 16%
• Symbolic Computation 16%
• Formal Verification 16%
• Mathematical Induction 16%