NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFEto Break Great Memory Wall with 10 ns of PGM-pulse, 1010Cycles of Endurance, and Decade Lifetime at 103 °C

E. R. Hsieh, J. K. Chang, T. Y. Tang, Y. J. Li, C. W. Liang, M. Y. Lin, S. Y. Huang, C. J. Su, J. C. Guo, S. S. Chung

研究成果: 書貢獻/報告類型會議論文篇章同行評審

1 引文 斯高帕斯(Scopus)

摘要

A novel concept of NVDimm-FE has been proposed to replace the DRAM position in the memory hierarchy. A high-density 3D architecture of 3-bit-per-CFE 2-transistors and n-ferroelectric-capacitances (3-bit/c 2TnCFE) array has been developed as a platform to realize this concept. Our results have shown that 3D 3-bit/c 2TnCFE array achieves 3.1V of the memory window, 62% of the program (PGM) efficiency, 10 ns of PGM-speed at 2.1MV/cm, excellent endurance up to 1010 times for each state of 3-bits per CFE (8 states), and retention for decade-lifetime prediction of the ferroelectric-NVMs at 103 °C. With the assistance of 3D integration of many vertical CFE layers, the 2TnCFE has been proved to be an ultra-high-density candidate of the NVDimm-FE to break the GREAT memory wall and boost high-performance computing efficiency in the future.

原文???core.languages.en_GB???
主出版物標題2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
發行者Institute of Electrical and Electronics Engineers Inc.
頁面359-360
頁數2
ISBN(電子)9781665497725
DOIs
出版狀態已出版 - 2022
事件2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States
持續時間: 12 6月 202217 6月 2022

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2022-June
ISSN(列印)0743-1562

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???event.eventtypes.event.conference???2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
國家/地區United States
城市Honolulu
期間12/06/2217/06/22

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