Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints

Yu Guang Chen, Wan Yu Wen, Yiyu Shi, Wing Kai Hon, Shih Chieh Chang

研究成果: 雜誌貢獻期刊論文同行評審

20 引文 斯高帕斯(Scopus)

摘要

In 3-D integrated circuits, through silicon via (TSV) is a critical enabling technique to provide vertical connections. However, it may suffer from many reliability issues such as undercut, misalignment, or random open defects. Various fault-tolerance mechanisms have been proposed in literature to improve yield, at the cost of significant area overhead. In this paper, we focus on the structure that uses one spare TSV for a group of original TSVs, and study the optimal assignment of spare TSVs under yield and timing constraints to minimize the total area overhead. We show that such problem can be modeled as a constrained graph decomposition problem. Two efficient heuristics are further developed to address this problem. Experimental results show that under the same yield and timing constraints, our heuristic can reduce the area overhead induced by the fault-tolerance mechanisms by up to 61%, compared with a seemingly more intuitive nearest-neighbor-based heuristic.

原文???core.languages.en_GB???
文章編號6998006
頁(從 - 到)577-588
頁數12
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
34
發行號4
DOIs
出版狀態已出版 - 1 4月 2015

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