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Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation
Hui Ru Jiang,
Jing Yang Jou
, Yao Wen Chang
電機工程學系
研究成果
:
雜誌貢獻
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會議論文
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9
引文 斯高帕斯(Scopus)
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Keyphrases
Lagrangian Relaxation
100%
Optimization Problem
100%
Noise Optimization
100%
Wire Sizing
100%
Gate Sizing
100%
Simultaneous Switching
100%
Performance Optimization
100%
Deep Submicron
50%
Workstation
50%
Memory Requirements
50%
Area Optimization
50%
Switching Behavior
50%
Physical Coupling
50%
Delay Optimization
50%
Existing Algorithms
50%
Linear Memory
50%
Circuit Component
50%
Switching Condition
50%
Noise Minimization
50%
Simultaneous Optimization
50%
Coupling Capacitance
50%
Power Optimization
50%
Computer Science
Lagrangian Relaxation
100%
Optimization Problem
100%
And Gate
100%
Performance Optimization
100%
Memory Requirement
50%
Power Optimization
50%
Coupling Capacitance
50%
Engineering
Lagrangian Relaxation
100%
Optimisation Problem
100%
Memory Requirement
50%
Physical Coupling
50%
Coupling Capacitance
50%