My-box representation for faulty CMOS circuits

J. E. Chen, C. L. Lee, W. Z. Shen

研究成果: 雜誌貢獻期刊論文同行評審

1 引文 斯高帕斯(Scopus)

摘要

A new logic element, My-box, is proposed to model the line faults (stuck-at-1 and stuck-at-0) and the transistor faults (stuck-on and stuck-open) of CMOS circuits, which consist of fully CMOS logic, pseudo nMOS logic, dynamic CMOS logic, clocked CMOS (C2MOS) logic, CMOS domino logic and NORA CMOS logic. It can also be used to model the faults and the functions of a transmission gate logic. A procedure is described to transform a transistor level CMOS circuit to a gate-level equivalent circuit which is composed of AND, OR and the My-box logic element. A fault collapsing procedure is also derived to determine the representative set of prime faults (RSPF) for the transformed gate-level circuit. By applying this procedure to ten benchmark circuits, the number of faults can be reduced to approximately 15% of the original total faults, if the ten benchmark circuits are implemented in the fully CMOS logic.

原文???core.languages.en_GB???
頁(從 - 到)225-232
頁數8
期刊IEE proceedings. Part G. Electronic circuits and systems
137
發行號3
DOIs
出版狀態已出版 - 1990

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