Multiplication of a Constant (2k ± 1) and Its Fast Hardware Implementation

Pin Chang Jui, Chin Long Wey, Muh Tian Shiue

研究成果: 雜誌貢獻期刊論文同行評審

摘要

Constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units and they are prevalent in modern VLSI designs. This study presents efficient algorithms and their fast hardware implementation for performing multiplying-by-(2k ± 1), or (2k ± 1)N, operation with additions. No multiplications are needed. The value of (2k ± 1)N can be computed by adding (±N) to its k-bits left-shifted value 2kN. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper presents the unit cells for additions (UCAs). Results show that the UCA-based RCA achieves 34 % faster than the FA-based RCA. Further, in order to improve the speed performance with lower hardware cost, this paper also presents a simple and modular hybrid adder with the proposed UCA concept, where the hybrid adder takes the lower-bit carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the proposed hybrid adder achieved speed performance improvement while maintaining its modular and regular structure.

原文???core.languages.en_GB???
頁(從 - 到)41-53
頁數13
期刊Journal of Signal Processing Systems
82
發行號1
DOIs
出版狀態已出版 - 1 1月 2016

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