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Multiple Retest Systems for Screening High-Quality Chips
Chung Huang Yeh, Jwu E. Chen
電機工程學系
研究成果
:
雜誌貢獻
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期刊論文
›
同行評審
3
引文 斯高帕斯（Scopus）
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Keyphrases
Test Yield
100%
Testing Model
66%
Digital Circuits
66%
Integrated Circuits
66%
Integrated Circuit Testing
66%
Test Quality
66%
Product Quality
33%
Slow Evolution
33%
Device Testing
33%
Semiconductor Manufacturing
33%
Quality Requirements
33%
Yield Improvement
33%
Model Calculation
33%
Performance Effectiveness
33%
Desired Quality
33%
Statistical Simulation Method
33%
Guard Band
33%
Testing Technology
33%
Zero Defects
33%
Lag behind
33%
High Quality Products
33%
Timing Accuracy
33%
Expected Quality
33%
Overall Profit
33%
Automated Test Equipment
33%
Reporting Lag
33%
Engineering
Integrated Circuit Testing
100%
Digital Integrated Circuits
100%
Integrated Circuit
100%
Test Result
50%
Semiconductor Manufacturing
50%
Product Quality
50%
Statistical Simulation Method
50%
Test Equipment
50%
High Quality Product
50%
Computer Science
Integrated Circuit
100%
Digital Integrated Circuits
100%
Product Quality
50%
Device under Test
50%
model based testing
50%
Desired Quality
50%
Quality Requirement
50%
Automated Test Equipment
50%
Physics
Integrated Circuit
100%
Material Science
Electronic Circuit
100%