TY - JOUR
T1 - Multilevel full-chip routing with testability and yield enhancement
AU - Li, Katherine Shu Min
AU - Lee, Chung Len
AU - Chang, Yao Wen
AU - Su, Chauchin
AU - Chen, Jwu E.
PY - 2005
Y1 - 2005
N2 - We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) The oscillation ring (OR) test and its diagnosis scheme for interconnect based on the IEEE P1500 are integrated into the multilevel routing framework to achieve testability enhancement. (2) We present a heuristic to balance routing congestion to optimize the multiple-fault probability, chemical mechanic polishing (CMP) and optical proximity correction (OPC) induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the MCNC benchmark circuits show that the proposed OR method achieves 100% fault coverage and the maximal diagnosis resolution for interconnects, and the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion. Compared with [14], the experimental results show that our router improves the maximal congestion by 1.24X - 6.11X in runtime speedup by 1.08X- - 7.66X, and improves the average congestion by 1.00X - 4.52X with the improved congestion deviation by 1.37X - 5.55X.
AB - We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) The oscillation ring (OR) test and its diagnosis scheme for interconnect based on the IEEE P1500 are integrated into the multilevel routing framework to achieve testability enhancement. (2) We present a heuristic to balance routing congestion to optimize the multiple-fault probability, chemical mechanic polishing (CMP) and optical proximity correction (OPC) induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the MCNC benchmark circuits show that the proposed OR method achieves 100% fault coverage and the maximal diagnosis resolution for interconnects, and the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion. Compared with [14], the experimental results show that our router improves the maximal congestion by 1.24X - 6.11X in runtime speedup by 1.08X- - 7.66X, and improves the average congestion by 1.00X - 4.52X with the improved congestion deviation by 1.37X - 5.55X.
KW - Multilevel routing
KW - Testability
KW - Yield
UR - http://www.scopus.com/inward/record.url?scp=30944441475&partnerID=8YFLogxK
U2 - 10.1145/1053355.1053362
DO - 10.1145/1053355.1053362
M3 - 會議論文
AN - SCOPUS:30944441475
SN - 1544-5631
SP - 29
EP - 36
JO - International Workshop on System Level Interconnect Prediction, SLIP
JF - International Workshop on System Level Interconnect Prediction, SLIP
T2 - SLIP'05 - 2005 International Workshop on System Level Interconnect Prediction
Y2 - 2 April 2005 through 3 April 2005
ER -