A module generator for the all-digital data recovery of a highspeed serial link, using an oversampling method, is proposed. The architecture of the proposed method is very regular and hence very suitable for standard cell implementation flow, which also makes it very suitable as a soft silicon intellectual property. This module generator can automatically generate the design parameters to deal with the oversampling architecture to meet different specifications. A design example, generated by the module generator, is implemented by using the TSMC 0.35 μm 1P4M cell library. The maximum performance of the design (without extra pipelining stages) can reach 2.09 Gbps with power consumption of 112.2 mW at 3.3 V.