Low voltage low power high-speed BiCMOS multiplier

Kuo Hsing Cheng; Yu Kwang Yeha; Farn Son Lian

Low voltage low power high-speed BiCMOS multiplier

Kuo Hsing Cheng, Yu Kwang Yeha, Farn Son Lian

電機工程學系

研究成果: 會議貢獻類型 › 會議論文 › 同行評審

摘要

A 16×16-bit parallel multiplier fabricated in a 1.0-μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

原文	???core.languages.en_GB???
頁面	p 4
出版狀態	已出版 - 1998
事件	Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology - Lisboa, Portugal 持續時間: 7 9月 1998 → 10 9月 1998

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???event.eventtypes.event.conference???	Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology
城市	Lisboa, Portugal
期間	7/09/98 → 10/09/98

引用此

@conference{d3403ccf7bcd4dc1a606f0784eb4db93,

title = "Low voltage low power high-speed BiCMOS multiplier",

abstract = "A 16×16-bit parallel multiplier fabricated in a 1.0-μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.",

author = "Cheng, {Kuo Hsing} and Yeha, {Yu Kwang} and Lian, {Farn Son}",

year = "1998",

language = "???core.languages.en_GB???",

pages = "p 4",

note = "Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology ; Conference date: 07-09-1998 Through 10-09-1998",

}

TY - CONF

T1 - Low voltage low power high-speed BiCMOS multiplier

AU - Cheng, Kuo Hsing

AU - Yeha, Yu Kwang

AU - Lian, Farn Son

PY - 1998

Y1 - 1998

N2 - A 16×16-bit parallel multiplier fabricated in a 1.0-μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

AB - A 16×16-bit parallel multiplier fabricated in a 1.0-μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

UR - http://www.scopus.com/inward/record.url?scp=0032265326&partnerID=8YFLogxK

M3 - 會議論文

AN - SCOPUS:0032265326

SP - p 4

T2 - Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology

Y2 - 7 September 1998 through 10 September 1998

ER -

Low voltage low power high-speed BiCMOS multiplier

摘要

???event.eventtypes.event.conference???

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