Low voltage low power high-speed BiCMOS multiplier

Kuo Hsing Cheng; Yu Kwang Yeha; Farn Sou Lian

doi:10.1109/ICECS.1998.814820

Low voltage low power high-speed BiCMOS multiplier

Kuo Hsing Cheng, Yu Kwang Yeha, Farn Sou Lian

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

原文	???core.languages.en_GB???
主出版物標題	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	49-50
頁數	2
ISBN（電子）	0780350081
DOIs	https://doi.org/10.1109/ICECS.1998.814820
出版狀態	已出版 - 1998
事件	5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 - Lisboa, Portugal 持續時間: 7 9月 1998 → 10 9月 1998

出版系列

名字	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
卷	2

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998
國家/地區	Portugal
城市	Lisboa
期間	7/09/98 → 10/09/98

存取文件

10.1109/ICECS.1998.814820

引用此

Cheng, K. H., Yeha, Y. K., & Lian, F. S. (1998). Low voltage low power high-speed BiCMOS multiplier. 於 Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (頁 49-50). 文章 814820 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; 卷 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.1998.814820

@inproceedings{949b4171d10547898b6a71e2110a3358,

title = "Low voltage low power high-speed BiCMOS multiplier",

abstract = "A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.",

author = "Cheng, {Kuo Hsing} and Yeha, {Yu Kwang} and Lian, {Farn Sou}",

note = "Publisher Copyright: {\textcopyright} 1998 IEEE.; 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 ; Conference date: 07-09-1998 Through 10-09-1998",

year = "1998",

doi = "10.1109/ICECS.1998.814820",

language = "???core.languages.en_GB???",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "49--50",

booktitle = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

}

Cheng, KH, Yeha, YK & Lian, FS 1998, Low voltage low power high-speed BiCMOS multiplier. 於 Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems., 814820, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 卷 2, Institute of Electrical and Electronics Engineers Inc., 頁 49-50, 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Lisboa, Portugal, 7/09/98. https://doi.org/10.1109/ICECS.1998.814820

Low voltage low power high-speed BiCMOS multiplier. / Cheng, Kuo Hsing; Yeha, Yu Kwang; Lian, Farn Sou.
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Institute of Electrical and Electronics Engineers Inc., 1998. p. 49-50 814820 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; 卷 2).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

TY - GEN

T1 - Low voltage low power high-speed BiCMOS multiplier

AU - Cheng, Kuo Hsing

AU - Yeha, Yu Kwang

AU - Lian, Farn Sou

PY - 1998

Y1 - 1998

N2 - A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

AB - A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

UR - http://www.scopus.com/inward/record.url?scp=46449123164&partnerID=8YFLogxK

U2 - 10.1109/ICECS.1998.814820

DO - 10.1109/ICECS.1998.814820

M3 - 會議論文篇章

AN - SCOPUS:46449123164

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

SP - 49

EP - 50

BT - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998

Y2 - 7 September 1998 through 10 September 1998

ER -

Cheng KH, Yeha YK, Lian FS. Low voltage low power high-speed BiCMOS multiplier. 於 Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Institute of Electrical and Electronics Engineers Inc. 1998. p. 49-50. 814820. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.1998.814820

Low voltage low power high-speed BiCMOS multiplier

摘要

出版系列

???event.eventtypes.event.conference???

存取文件

指紋

引用此