Low supply voltage and multiphase all-digital crystal-less clock generator

Yo Hao Tu, Jen Chieh Liu, Kuo Hsing Cheng, Chi Yang Chang

研究成果: 雜誌貢獻期刊論文同行評審

3 引文 斯高帕斯(Scopus)


A multiphase all-digital crystal-less clock generator (CLCG) with an interpolating digital controlled oscillator (DCO) that achieves an operating frequency of 500 MHz with 10-phase outputs is proposed. The CLCG adopts a specific temperature coefficient of a time-to-digital convertor (TDC) to create a positive or negative temperature coefficient and compensates for the DCO frequency drift. A time amplifier (TA) can extend the timing resolution of the TDC and reduce the effects of process variations in order to tune the TA gains. The frequency compensator adopts the frequency difference between the ring oscillator and DCO to reduce the frequency drift. The frequency accuracy is 69 ppm/°C from - 20 to 80°C. The root mean square jitter and output phase noise are 3.86 ps and - 100.36 dBc/Hz at 1 MHz, respectively. The core area of the test chip is 350 × 420 μm2 in a 65-nm CMOS process. At a supply voltage of 0.6 V, the power consumption is 1.8 mW for the 5 Gb/s clocking system.

頁(從 - 到)720-725
期刊IET Circuits, Devices and Systems
出版狀態已出版 - 1 11月 2018


深入研究「Low supply voltage and multiphase all-digital crystal-less clock generator」主題。共同形成了獨特的指紋。