Low-power variable-length fast Fourier transform processor

Y. T. Lin, P. Y. Tsai, T. D. Chiueh

研究成果: 雜誌貢獻期刊論文同行評審

84 引文 斯高帕斯(Scopus)

摘要

Fast Fourier transform (FFT) processing is one of the key procedures in the popular orthogonal frequency division multiplexing (OFDM) communication systems. Structured pipeline architectures and low power consumption are the main concerns for its VLSI implementation. In the paper, the authors report a variable-length FFT processor design that is based on a radix-2/4/8 algorithm and a single-path delay feedback architecture. The processor can be used in various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T), asymmetric digital subscriber loop (ADSL) and very-high-speed digital subscriber loop (VDSL). To reduce power consumption and chip area, special current-mode SRAMs are adopted to replace shift registers in the delay lines. In addition, techniques including complex multipliers containing three real multiplications, and reduced sine/cosine tables are adopted. The chip is fabricated using a 0.35 μm CMOS process and it measures 3900 μm × 5500 μm. According to the measured results, the 2048-point FFT operation can function correctly up to 45 MHz with a 3.3 V supply voltage and power consumption of 640 mW. In low-power operation, when the supply voltage is scaled down to 2.3 V, the processor consumes 176 mW when it runs at 17.8 MHz.

原文???core.languages.en_GB???
頁(從 - 到)499-506
頁數8
期刊IEE Proceedings: Computers and Digital Techniques
152
發行號4
DOIs
出版狀態已出版 - 7月 2005

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