Low power multi-lane MIPI CSI-2 receiver design and hardware implementations

Yueh Chuan Lu, Zong Yi Chen, Pao Chi Chang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

3 引文 斯高帕斯(Scopus)

摘要

This paper proposes a low power multi-Lane Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) receiver architecture which adopts an 8-Byte parallel CSI protocol layer for hardware implementations. The proposed scheme can work in environment with 4 data Lanes and 1 Gb/s per data Lane, i.e. with maximum data rate 4 Gb/s, at 62.5 MHz which increases logic operations from 8 ns (125 MHz) to 16 ns (62.5 MHz) without throughput degradation. Therefore, the supply voltage (1.2 V) can be reduced and the power consumption can also be reduced. The proposed architecture is implemented by 0.13μm CMOS technology and the total gate count is 32.7K. It not only reduces the operating clock rate but also reduces more than 37%∼43% logic power consumption measured in chip.

原文???core.languages.en_GB???
主出版物標題2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
頁面199-200
頁數2
DOIs
出版狀態已出版 - 2013
事件2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013 - Hsinchu, Taiwan
持續時間: 3 6月 20136 6月 2013

出版系列

名字Proceedings of the International Symposium on Consumer Electronics, ISCE

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???event.eventtypes.event.conference???2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
國家/地區Taiwan
城市Hsinchu
期間3/06/136/06/13

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