Low-jitter and low-power phase-locked loop design

This paper describes a design of digital phase-locked loop (DPLL), which has low-power consumption and low jitter feature. Novel voltage controlled oscillator (VCO) and phase frequency detector (PFD) are proposed to reduce the total power consumption and phase error of the DPLL. The proposed VCO has low power consumption, and the PFD is a `three-state' structure with dead zone is 5 ps. The power consumption of the proposed DPLL is lower than 6.7 mW, and the output-frequency range of the oscillator is from 200 MHz to 650 MHz. The worst-case cycle jitter is lower than 160 ps, and long-term jitter is lower than 220 ps. We confirm the results based on 0.5 um CMOS technology and 3 V supply voltage.