@article{e1e65a2990814c8f8aae8bd327d70e09,
title = "Low-cost self-test techniques for small RAMs in SOCs using enhanced IEEE 1500 test wrappers",
abstract = "This paper proposes an enhanced IEEE 1500 test wrapper to support the testing and diagnosis of the single-port or multi-port RAM core attached to the enhanced IEEE 1500 test wrapper without incurring large area overhead to small memories. Effective test time reduction techniques for the proposed test scheme are also proposed. Simulation results show that the additional area cost for implementing the enhanced IEEE 1500 test wrapper is only about 0.58% for a 64 K-bit single-port RAM and only 0.57% for a 64 K-bit two-port RAM in 90-nm technology.",
keywords = "built-in self-test (BIST), IEEE 1500, multi-port RAM, random access memory (RAM), system-on-chip (SOC)",
author = "Huang, {Yu Jen} and Li, {Jin Fu}",
note = "Funding Information: Manuscript received February 20, 2011; revised May 15, 2011; accepted August 12, 2011. Date of publication October 06, 2011; date of current version July 27, 2012. A portion of this work has been published in IEEE International SOC Conference (SOCC), 2010. This work was supported in part by National Science Council, Taiwan, under Contract NSC 97-2221-E-008-094-MY3 and NSC 97-2221-E-008-095-MY3, Taiwan.",
year = "2012",
doi = "10.1109/TVLSI.2011.2165568",
language = "???core.languages.en_GB???",
volume = "20",
pages = "2123--2127",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
number = "11",
}