Low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

Tsung Han Tsai; Liang Gee Chen; Sheng Chieh Huang; Hao Chieh Chang

Low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

Tsung Han Tsai, Liang Gee Chen, Sheng Chieh Huang, Hao Chieh Chang

電機工程學系

研究成果: 雜誌貢獻 › 會議論文 › 同行評審

1 引文斯高帕斯（Scopus）

摘要

The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-fourths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration.

原文	???core.languages.en_GB???
頁（從 - 到）	65-68
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	4
出版狀態	已出版 - 1998
事件	Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA 持續時間: 31 5月 1998 → 3 6月 1998

引用此

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AB - The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-fourths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration.

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Y2 - 31 May 1998 through 3 June 1998

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Low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

摘要

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