In this paper, a low complexity 8 × 8 MIMO detector supporting QPSK, 16-QAM, and 64-QAM is presented. A breadth-first type known as distributed K-best (DKB) algorithm is applied in the design. Compared with the conventional K-best algorithm, the DKB reduces the number of visited nodes at each layer from K√M to 2K - 1, where K and M are the quantity of candidates and constellation size, respectively. To further reduce power consumption, a shift multiplier which simply operates bits shifting and additions is proposed to replace the conventional multiplier. In addition, the proposed multi-stage circuit architecture only requires K clock cycles to find the best K candidates, and the sorting circuits for the conventional K-best can be avoided in our design. The proposed 8 × 8 MIMO detector has been implemented by a 90-nm CMOS technology with a core area of 0.99 × 0.99mm2. The average power consumption is about 17.2 mW at 74 MHz and 1 V supply voltage.