In this chapter, we discuss the reliability issues about 3D-ICs fabrication process under technologies nowadays, and propose possible solutions to address the problems. In Section 9.1, we lay down the reasons in detail as to why there are seldom 3D-IC products today versus the problem of low yield of TSVs. Section 9.2 shows two major fault-tolerant structures, double TSV and shared-spare TSV, to improve the chip yield. The fault-tolerant design constraints then are addressed in Section 9.3. In Section 9.4, we address the problem of spare TSV assignment, and proposed two heuristics to optimize area overhead under given constraints. A fault-tolerance clock network then is discussed in Section 9.5 with two different structures. Concluding remarks are given in Section 9.6.