LDS-ATPG: An automatic test pattern generation system for combinational VLSI circuits

Sen Chung Jiang; Chung Len Lee; Wen Zen Shen; Jwu E. Chen; Ching Ping Wu

LDS-ATPG: An automatic test pattern generation system for combinational VLSI circuits

Sen Chung Jiang, Chung Len Lee, Wen Zen Shen, Jwu E. Chen, Ching Ping Wu

電機工程學系

研究成果: 會議貢獻類型 › 會議論文 › 同行評審

1 引文斯高帕斯（Scopus）

摘要

An ATPG (automatic test pattern generation) system that consists of three optional test pattern generators and a fault simulator is presented. The three test pattern generators include a random pattern generator with the linear feedback shift register (LFSR) technique, a pseudorandom pattern generator, DISRUPT, and a deterministic test pattern generator, SLOPE1, which employs dynamic compaction to increase the fault coverage. The generators, together with a fault simulator, ACCEPT, generate test sets much smaller than those reported for other ATG systems while achieving the same or even better fault coverage with comparable system run times.

原文	???core.languages.en_GB???
頁面	159-161
頁數	3
出版狀態	已出版 - 1989
事件	International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan 持續時間: 17 5月 1989 → 19 5月 1989

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???event.eventtypes.event.conference???	International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers
城市	Taipei, Taiwan
期間	17/05/89 → 19/05/89

引用此

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title = "LDS-ATPG: An automatic test pattern generation system for combinational VLSI circuits",

abstract = "An ATPG (automatic test pattern generation) system that consists of three optional test pattern generators and a fault simulator is presented. The three test pattern generators include a random pattern generator with the linear feedback shift register (LFSR) technique, a pseudorandom pattern generator, DISRUPT, and a deterministic test pattern generator, SLOPE1, which employs dynamic compaction to increase the fault coverage. The generators, together with a fault simulator, ACCEPT, generate test sets much smaller than those reported for other ATG systems while achieving the same or even better fault coverage with comparable system run times.",

author = "Jiang, {Sen Chung} and Lee, {Chung Len} and Shen, {Wen Zen} and Chen, {Jwu E.} and Wu, {Ching Ping}",

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T1 - LDS-ATPG

T2 - International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers

AU - Jiang, Sen Chung

AU - Lee, Chung Len

AU - Shen, Wen Zen

AU - Chen, Jwu E.

AU - Wu, Ching Ping

PY - 1989

Y1 - 1989

N2 - An ATPG (automatic test pattern generation) system that consists of three optional test pattern generators and a fault simulator is presented. The three test pattern generators include a random pattern generator with the linear feedback shift register (LFSR) technique, a pseudorandom pattern generator, DISRUPT, and a deterministic test pattern generator, SLOPE1, which employs dynamic compaction to increase the fault coverage. The generators, together with a fault simulator, ACCEPT, generate test sets much smaller than those reported for other ATG systems while achieving the same or even better fault coverage with comparable system run times.

AB - An ATPG (automatic test pattern generation) system that consists of three optional test pattern generators and a fault simulator is presented. The three test pattern generators include a random pattern generator with the linear feedback shift register (LFSR) technique, a pseudorandom pattern generator, DISRUPT, and a deterministic test pattern generator, SLOPE1, which employs dynamic compaction to increase the fault coverage. The generators, together with a fault simulator, ACCEPT, generate test sets much smaller than those reported for other ATG systems while achieving the same or even better fault coverage with comparable system run times.

UR - http://www.scopus.com/inward/record.url?scp=0024888106&partnerID=8YFLogxK

M3 - 會議論文

AN - SCOPUS:0024888106

SP - 159

EP - 161

Y2 - 17 May 1989 through 19 May 1989

ER -

LDS-ATPG: An automatic test pattern generation system for combinational VLSI circuits

摘要

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