摘要
An ATPG (automatic test pattern generation) system that consists of three optional test pattern generators and a fault simulator is presented. The three test pattern generators include a random pattern generator with the linear feedback shift register (LFSR) technique, a pseudorandom pattern generator, DISRUPT, and a deterministic test pattern generator, SLOPE1, which employs dynamic compaction to increase the fault coverage. The generators, together with a fault simulator, ACCEPT, generate test sets much smaller than those reported for other ATG systems while achieving the same or even better fault coverage with comparable system run times.
原文 | ???core.languages.en_GB??? |
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頁面 | 159-161 |
頁數 | 3 |
出版狀態 | 已出版 - 1989 |
事件 | International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan 持續時間: 17 5月 1989 → 19 5月 1989 |
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???event.eventtypes.event.conference??? | International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers |
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城市 | Taipei, Taiwan |
期間 | 17/05/89 → 19/05/89 |