LDS-ATPG: An automatic test pattern generation system for combinational VLSI circuits

Sen Chung Jiang, Chung Len Lee, Wen Zen Shen, Jwu E. Chen, Ching Ping Wu

研究成果: 會議貢獻類型會議論文同行評審

1 引文 斯高帕斯(Scopus)

摘要

An ATPG (automatic test pattern generation) system that consists of three optional test pattern generators and a fault simulator is presented. The three test pattern generators include a random pattern generator with the linear feedback shift register (LFSR) technique, a pseudorandom pattern generator, DISRUPT, and a deterministic test pattern generator, SLOPE1, which employs dynamic compaction to increase the fault coverage. The generators, together with a fault simulator, ACCEPT, generate test sets much smaller than those reported for other ATG systems while achieving the same or even better fault coverage with comparable system run times.

原文???core.languages.en_GB???
頁面159-161
頁數3
出版狀態已出版 - 1989
事件International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan
持續時間: 17 5月 198919 5月 1989

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???event.eventtypes.event.conference???International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers
城市Taipei, Taiwan
期間17/05/8919/05/89

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