As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Some of the previous techniques such as net ordering, shield insertion, twisted-bundle layout structure, and interdigitated techniques are either inefficient or incur too much area penalty. In this paper, we present two techniques - ground-aware net routing and source pin positioning - that can reduce inductance effectively without incurring area penalty. In order to prove the effectiveness of our techniques, we use the famous 3D field-solver FastHenry to extract inductances and verify our results. All simulation results show that our proposed techniques can significantly reduce inductances without incurring area penalty.
|出版狀態||已出版 - 2004|
|事件||Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan|
持續時間: 27 1月 2004 → 30 1月 2004
|???event.eventtypes.event.conference???||Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004|
|期間||27/01/04 → 30/01/04|