Latched CMOS Differential Logic (LCDL) for Complex High-Speed VLSI

Chung Yu Wu, Kuo Hsing Cheng

研究成果: 雜誌貢獻期刊論文同行評審

14 引文 斯高帕斯(Scopus)

摘要

A new CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate, and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results have verified the high speed and race-free performance of the proposed LCDL.

原文???core.languages.en_GB???
頁(從 - 到)1324-1328
頁數5
期刊IEEE Journal of Solid-State Circuits
26
發行號9
DOIs
出版狀態已出版 - 9月 1991

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