Innovative Practice on Wafer Test Innovations

Dyi Chung Hu, Hirohito Hashimoto, Li Fong Tseng, Ken Chau Cheung Cheng, Katherine Shu-Min Li, Sying Jyan Wang, Sean Y.S. Chen, Jwu E. Chen, Clark Liu, Andrew Huang

研究成果: 書貢獻/報告類型會議論文篇章同行評審


Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.

主出版物標題Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020
發行者IEEE Computer Society
出版狀態已出版 - 4月 2020
事件38th IEEE VLSI Test Symposium, VTS 2020 - San Diego, United States
持續時間: 5 4月 20208 4月 2020


名字Proceedings of the IEEE VLSI Test Symposium


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國家/地區United States
城市San Diego


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