@inproceedings{35f0d64e9fbb44209e142c872ae38391,
title = "Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design",
abstract = "This paper presents an approach of incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter (APF) design. Even when the three-phase source voltages are unbalanced and/or distorted and supply to a nonlinear load, the described compensation strategy can compensate the harmonic and neutral current, and thus improve the power factor. After verifying the efficiency of compensation strategy, the APF control strategy is embedded into the digital signal processor (DSP) to verify the feasibility of the proposed strategy on hardware in the loop (HIL) structure. Results show that the proposed approach is effective for shunt APF design.",
keywords = "Active power filter, Digital signal processor, Hardware-in-the-loop, Harmonics, Real-time simulation",
author = "Hong, {R. C.} and Chang, {G. W.} and Chao, {C. Y.} and Chu, {Y. b.} and Chen, {C. I.}",
year = "2010",
doi = "10.1109/ICIEA.2010.5517124",
language = "???core.languages.en_GB???",
isbn = "9781424450466",
series = "Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010",
pages = "492--497",
booktitle = "Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010",
note = "5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010 ; Conference date: 15-06-2010 Through 17-06-2010",
}