Improvement of conditional sum adder for low power applications

Kuo Hsing Cheng, Shu Min Chiang, Shun Wen Cheng

研究成果: 雜誌貢獻會議論文同行評審

12 引文 斯高帕斯(Scopus)

摘要

This work describes a new conditional-sum addition rule for low power applications. This conditional sum adder is especially attractive for implementing high-speed arithmetic systems. The new conditional sum addition rule can reduce the internal nodes and multiplexer numbers of the adder design. Various supply voltages and circuit structures are used to implement the new conditional sum adders. It's shown that about 10% to 25% power-delay product is saved.

原文???core.languages.en_GB???
頁(從 - 到)131-134
頁數4
期刊Proceedings of the Annual IEEE International ASIC Conference and Exhibit
出版狀態已出版 - 1998
事件Proceedings of the 1998 11th Annual IEEE International ASIC Conference - Rochester, NY, USA
持續時間: 13 9月 199816 9月 1998

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