Implementation of FPGA-based Accelerator for Deep Neural Networks

Tsung Han Tsai, Yuan Chen Ho, Ming Hwa Sheu

研究成果: 書貢獻/報告類型會議論文篇章同行評審

21 引文 斯高帕斯(Scopus)

摘要

At present, there are many researches on deep neural network (DNN) applied in life. In the task of object recognition, deep convolutional neural network (CNN) has a good performance, but it relies on GPU to solve a large number of complex operations. Thus the hardware accelerator of DNN is concerned by many people. In order to implement the DNN model on hardware, complex connection relationship and memory usage scheduling are needed. This paper presnets the design of FPGA-based accelerator for DNN. The proposed architecture is implemented on Xilinx Zynq-7020 FPGA. It takes the advantages of low latency and low usage in the task of MNIST digital identification, and keeps the 96 % recognition rate.

原文???core.languages.en_GB???
主出版物標題Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728100739
DOIs
出版狀態已出版 - 4月 2019
事件22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 - Cluj-Napoca, Romania
持續時間: 24 4月 201926 4月 2019

出版系列

名字Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019

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???event.eventtypes.event.conference???22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
國家/地區Romania
城市Cluj-Napoca
期間24/04/1926/04/19

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