@inproceedings{d23cff6d1ce74156bfe16487bd6b6a53,
title = "Implementation of FPGA-based Accelerator for Deep Neural Networks",
abstract = "At present, there are many researches on deep neural network (DNN) applied in life. In the task of object recognition, deep convolutional neural network (CNN) has a good performance, but it relies on GPU to solve a large number of complex operations. Thus the hardware accelerator of DNN is concerned by many people. In order to implement the DNN model on hardware, complex connection relationship and memory usage scheduling are needed. This paper presnets the design of FPGA-based accelerator for DNN. The proposed architecture is implemented on Xilinx Zynq-7020 FPGA. It takes the advantages of low latency and low usage in the task of MNIST digital identification, and keeps the 96 % recognition rate.",
keywords = "CNN, DNN, FPGA, hardware accelerator, low utilization",
author = "Tsai, {Tsung Han} and Ho, {Yuan Chen} and Sheu, {Ming Hwa}",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 ; Conference date: 24-04-2019 Through 26-04-2019",
year = "2019",
month = apr,
doi = "10.1109/DDECS.2019.8724665",
language = "???core.languages.en_GB???",
series = "Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019",
}