Identifying invalid states for sequential circuit test generation

Hsing Chung Liang, Chung Len Lee, Jwu E. Chen

研究成果: 雜誌貢獻期刊論文同行評審

7 引文 斯高帕斯(Scopus)


For sequential circuit test pattern generation incorporating backward justification, we need to justify the values on flip-flops to activate and propagate fault effects. This takes much time when the values to be justified on flip-flops appear to be invalid states. Hence, it is desirable to know invalid states, either dynamically during the justification process or statically before proceeding to test generation. This paper proposes algorithms to identify, before test generation, invalid states for sequential circuits without reset states. The first algorithm explores all valid states from an unknown initial state to search the complete set of invalid states. The second algorithm finds the complete set of invalid states from searching the reachable states for each state. The third algorithm searches the invalid states which are required for test generation to help stop justification early by analyzing dependency among flip-flops to simulate each partial circuit. Experimental results on ISCAS benchmark circuits show that the algorithms can identify invalid states in short time. The obtained invalid states were also used in test generation, and it was shown that they improved test generation significantly in test generation time, fault coverage, and detection efficiency, especially for larger circuits and for those that were difficult to generate.

頁(從 - 到)1025-1033
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
出版狀態已出版 - 1997


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