@inproceedings{36c79043c00e4f9f842692729f705c39,
title = "High voltage power MOSFET with reduced JFET area design",
abstract = "A high voltage power vertical double-diffused MOSFET with reduced JFET area by using an overall implantation was discussed. The reduced JFET area realizes a low gate charge and a high switching speed, due to the reduction of the gate-drain overlapped area. The measured gate-drain charge and gate charge can be improved by 61.1% and 71.8 %, respectively. The F.O.M of the proposed device and the conventional one is 64.4 nΩ×C and 190.9 nΩ×C, respectively. We also discussed the reliability issue and compared the avalanche capability to the proposed structure and the conventional device. The ruggedness of the proposed devices can be improved by a higher cell density design with a planar oxide self align p+ implantation process.",
keywords = "Figure of merit (F.O.M.), Gate charge, Power VDMOSFET, Unclamped inductive load switching (UIS)",
author = "Chien, {Feng Tso} and Li, {Tien Chun} and Lai, {Ping Hung} and Liao, {Chien Nan} and Tsai, {Yao Tsung}",
year = "2010",
doi = "10.1109/PEDG.2010.5545763",
language = "???core.languages.en_GB???",
isbn = "9781424456703",
series = "2nd International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2010",
pages = "526--529",
booktitle = "2nd International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2010",
note = "2nd International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2010 ; Conference date: 16-06-2010 Through 18-06-2010",
}