High-speed four-phase CMOS logic for complex high-speed VLSI

Chung Yu Wu, Kuo Hsing Cheng, Jinn Shyan Wang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

In this paper, a new four-phase dynamic logic, called the high-speed precharge-discharge CMOS logic (HS-PDCMOS logic) is proposed and analyzed. Basically the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus a complex function can be implemented within a single gate and achieve a high operation speed. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to verify partly the results of circuit analysis and simulation. It is shown that the HS-PDCMOS has an operation speed about 2.5 to 3 times higher than the conventional four-phase dynamic logic. Moreover, the new logic has no problems of clock skew, race, and charge redistribution.

原文???core.languages.en_GB???
主出版物標題1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1288-1291
頁數4
ISBN(電子)0780305930
DOIs
出版狀態已出版 - 1992
事件1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
持續時間: 10 5月 199213 5月 1992

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
3
ISSN(列印)0271-4310

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???event.eventtypes.event.conference???1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
國家/地區United States
城市San Diego
期間10/05/9213/05/92

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