High-performance double-channel poly-silicon thin-film transistor with raised drain and reduced drain electric field structures

Feng Tso Chien, Chien Nan Liao, Chin Mu Fang, Yao Tsung Tsai

研究成果: 雜誌貢獻期刊論文同行評審

5 引文 斯高帕斯(Scopus)

摘要

In this paper, a high-performance single-gate double-channel polycrystalline-silicon thin-film transistor (DCTFT) is proposed and experimentally demonstrated for the first time. Two thin channels, accompanied with a raised source/drain (S/D) area, an offset structure, a drain field plate, and a field-induced drain region, are used in this device, allowing a lower S/D resistance and a better device performance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability, such as threshold voltage shift and drain on-current degradation under a high gate bias, is also improved by the design of two channels and the reduced drain electric field structures. The lower drain electric field of the DCTFT is also beneficial to scaling down the device for a better performance.

原文???core.languages.en_GB???
頁(從 - 到)441-447
頁數7
期刊IEEE Transactions on Electron Devices
56
發行號3
DOIs
出版狀態已出版 - 2009

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