High efficient 3-input XOR for low-voltage low-power high-speed applications

Kuo Hsing Cheng, Ven Chieh Hsieh

研究成果: 書貢獻/報告類型會議論文篇章同行評審

5 引文 斯高帕斯(Scopus)

摘要

A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.

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主出版物標題AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
發行者Institute of Electrical and Electronics Engineers Inc.
頁面166-169
頁數4
ISBN(列印)0780357051, 9780780357051
DOIs
出版狀態已出版 - 1999
事件1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
持續時間: 23 8月 199925 8月 1999

出版系列

名字AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

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???event.eventtypes.event.conference???1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
國家/地區Korea, Republic of
城市Seoul
期間23/08/9925/08/99

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