@inproceedings{15005c06116a400c98f4c4d08e08df6d,
title = "High efficient 3-input XOR for low-voltage low-power high-speed applications",
abstract = "A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.",
author = "Cheng, {Kuo Hsing} and Hsieh, {Ven Chieh}",
note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 ; Conference date: 23-08-1999 Through 25-08-1999",
year = "1999",
doi = "10.1109/APASIC.1999.824054",
language = "???core.languages.en_GB???",
isbn = "0780357051",
series = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "166--169",
booktitle = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",
}