High efficiency architecture of fast block motion estimation with real-time QFHD on H.264 video coding

Tsai Tsung-Han, Pan Yu-Nan

研究成果: 書貢獻/報告類型會議論文篇章同行評審

3 引文 斯高帕斯(Scopus)

摘要

The H.264/AVC inter-prediction is performed for Variable Block-Size Motion Estimation (VBSME) such as 16×16, 16×8, 8×16, 8×8, 8×4, 4×8 and 4×4, it cause the high complexity for H.264 Motion Estimation (ME). This investigation develops an architecture for a combined fast motion estimation algorithm with Edge Information Mode Decision (EIMD) and Predict Hexagon Search (PHS). Compared with other popular ME architecture, the proposed architecture has a large search range and low processing frequency. For the general specification of SDTV (720×480) with 4 reference frames, search range 256×256, the proposed architecture needs only 18.66MHz. For the very high specification of QFHD (3840×2160) with 1 reference frame, search range 256×256, the proposed architecture only requires 112MHz. The gate count of the proposed architecture is 300K, and the memory usage is 12.6 KB.

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主出版物標題Proceedings - 10th IEEE International Symposium on Multimedia, ISM 2008
頁面124-129
頁數6
DOIs
出版狀態已出版 - 2008
事件10th IEEE International Symposium on Multimedia, ISM 2008 - Berkeley, CA, United States
持續時間: 15 12月 200817 12月 2008

出版系列

名字Proceedings - 10th IEEE International Symposium on Multimedia, ISM 2008

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???event.eventtypes.event.conference???10th IEEE International Symposium on Multimedia, ISM 2008
國家/地區United States
城市Berkeley, CA
期間15/12/0817/12/08

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