High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning

E. R. Hsieh, X. Zheng, M. Nelson, B. Q. Le, H. S.P. Wong, S. Mitra, S. Wong, M. Giordano, B. Hodson, A. Levy, S. K. Osekowsky, R. M. Radway, Y. C. Shih, W. Wan, T. F. Wu

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21 引文 斯高帕斯(Scopus)

摘要

We present the first demonstration of 1T4R Resistive RAM (RRAM) array storing two bits per RRAM cell. Our HfO2- based RRAM is built using a logic foundry technology that is fully compatible with the CMOS back-end process. We present a new approach to program RRAM cells using gradual SET/RESET pulses while minimizing disturbances on adjacent cells (belonging to the same 1T4R RRAM structure) - this new approach makes our multiple-bits-per-cell 1T4R RRAM array demonstration possible. We report over 106 cycles of endurance and a projected 10-year retention at 120°C. Using measured data from our 2 bits- per-cell 1T4R RRAM array, we analyze multiple deep learning applications and demonstrate high degrees of inference accuracy (within 0.01% of ideal values).

原文???core.languages.en_GB???
主出版物標題2019 IEEE International Electron Devices Meeting, IEDM 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728140315
DOIs
出版狀態已出版 - 12月 2019
事件65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States
持續時間: 7 12月 201911 12月 2019

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2019-December
ISSN(列印)0163-1918

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???event.eventtypes.event.conference???65th Annual IEEE International Electron Devices Meeting, IEDM 2019
國家/地區United States
城市San Francisco
期間7/12/1911/12/19

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