High accuracy jitter measurement using cyclic pulse width modulation structure

Kuo Hsing Cheng; Shu Yu Jiang

doi:10.1109/VDAT.2005.1500010

High accuracy jitter measurement using cyclic pulse width modulation structure

Kuo Hsing Cheng, Shu Yu Jiang

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

1 引文斯高帕斯（Scopus）

摘要

For high-speed circuit testing, traditional ways are not enough in measuring the clock jitter. The probe's loading effect would distort the tested clock signal and change the measurement result. Even some BIST techniques can release this problem. There is still a conflict between the circuit area and the timing resolution in the existing BIST techniques. The cyclic pulse width modulation structure is used to release this problem. The hardware overhead problem is released and the demanded resolution also can be reached. Furthermore, the effect of the PVTL is also released. The simulation result is based on TSMC 0.25um CMOS process. The selectable resolution is from 9ps to 20ps and the area is 0.039mm².

原文	???core.languages.en_GB???
主出版物標題	2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
頁面	24-27
頁數	4
DOIs	https://doi.org/10.1109/VDAT.2005.1500010
出版狀態	已出版 - 2005
事件	2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan 持續時間: 27 4月 2005 → 29 4月 2005

出版系列

名字	2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
卷	2005

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
國家/地區	Taiwan
城市	Hsinchu
期間	27/04/05 → 29/04/05

存取文件

10.1109/VDAT.2005.1500010

引用此

Cheng, K. H., & Jiang, S. Y. (2005). High accuracy jitter measurement using cyclic pulse width modulation structure. 於 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) (頁 24-27). 文章 1500010 (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); 卷 2005). https://doi.org/10.1109/VDAT.2005.1500010

@inproceedings{8e7b340c64e74174b866bdabd3d76fbc,

title = "High accuracy jitter measurement using cyclic pulse width modulation structure",

abstract = "For high-speed circuit testing, traditional ways are not enough in measuring the clock jitter. The probe's loading effect would distort the tested clock signal and change the measurement result. Even some BIST techniques can release this problem. There is still a conflict between the circuit area and the timing resolution in the existing BIST techniques. The cyclic pulse width modulation structure is used to release this problem. The hardware overhead problem is released and the demanded resolution also can be reached. Furthermore, the effect of the PVTL is also released. The simulation result is based on TSMC 0.25um CMOS process. The selectable resolution is from 9ps to 20ps and the area is 0.039mm2.",

author = "Cheng, {Kuo Hsing} and Jiang, {Shu Yu}",

year = "2005",

doi = "10.1109/VDAT.2005.1500010",

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isbn = "0780390601",

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booktitle = "2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)",

note = "2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) ; Conference date: 27-04-2005 Through 29-04-2005",

}

Cheng, KH & Jiang, SY 2005, High accuracy jitter measurement using cyclic pulse width modulation structure. 於 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)., 1500010, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT), 卷 2005, 頁 24-27, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT), Hsinchu, Taiwan, 27/04/05. https://doi.org/10.1109/VDAT.2005.1500010

High accuracy jitter measurement using cyclic pulse width modulation structure. / Cheng, Kuo Hsing; Jiang, Shu Yu.
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT). 2005. p. 24-27 1500010 (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); 卷 2005).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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AU - Cheng, Kuo Hsing

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PY - 2005

Y1 - 2005

N2 - For high-speed circuit testing, traditional ways are not enough in measuring the clock jitter. The probe's loading effect would distort the tested clock signal and change the measurement result. Even some BIST techniques can release this problem. There is still a conflict between the circuit area and the timing resolution in the existing BIST techniques. The cyclic pulse width modulation structure is used to release this problem. The hardware overhead problem is released and the demanded resolution also can be reached. Furthermore, the effect of the PVTL is also released. The simulation result is based on TSMC 0.25um CMOS process. The selectable resolution is from 9ps to 20ps and the area is 0.039mm2.

AB - For high-speed circuit testing, traditional ways are not enough in measuring the clock jitter. The probe's loading effect would distort the tested clock signal and change the measurement result. Even some BIST techniques can release this problem. There is still a conflict between the circuit area and the timing resolution in the existing BIST techniques. The cyclic pulse width modulation structure is used to release this problem. The hardware overhead problem is released and the demanded resolution also can be reached. Furthermore, the effect of the PVTL is also released. The simulation result is based on TSMC 0.25um CMOS process. The selectable resolution is from 9ps to 20ps and the area is 0.039mm2.

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BT - 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)

T2 - 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)

Y2 - 27 April 2005 through 29 April 2005

ER -

High accuracy jitter measurement using cyclic pulse width modulation structure

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