@inproceedings{634434e7b775413b98f220103c8cf6d4,
title = "Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability",
abstract = "Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. Ion/Ioff ratios higher than 107 and 106 for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.",
author = "Su, {C. J.} and Hong, {T. C.} and Tsou, {Y. C.} and Hou, {F. J.} and Sung, {P. J.} and Yeh, {M. S.} and Wan, {C. C.} and Kao, {K. H.} and Tang, {Y. T.} and Chiu, {C. H.} and Wang, {C. J.} and Chung, {S. T.} and You, {T. Y.} and Huang, {Y. C.} and Wu, {C. T.} and Lin, {K. L.} and Luo, {G. L.} and Huang, {K. P.} and Lee, {Y. J.} and Chao, {T. S.} and Wu, {W. F.} and Huang, {G. W.} and Shieh, {J. M.} and Yeh, {W. K.} and Wang, {Y. H.}",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 63rd IEEE International Electron Devices Meeting, IEDM 2017 ; Conference date: 02-12-2017 Through 06-12-2017",
year = "2018",
month = jan,
day = "23",
doi = "10.1109/IEDM.2017.8268396",
language = "???core.languages.en_GB???",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "15.4.1--15.4.4",
booktitle = "2017 IEEE International Electron Devices Meeting, IEDM 2017",
}