Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array

E. R. Hsieh, X. Zheng, B. Q. Le, Y. C. Shih, R. M. Radway, M. Nelson, S. Mitra, S. Wong

研究成果: 雜誌貢獻期刊論文同行評審

24 引文 斯高帕斯(Scopus)

摘要

We demonstrate a 1MBit array of 1-Transistor-8-Resistive RAM (1T8R) memory fabricated using a foundry logic technology. Using a gradual SET/RESET programming scheme, sixteen conductance levels are stored in each RRAM, achieving 1T8R array with 4 bits per RRAM. We report SET/RESET endurance of 100K cycles and 10-year retention at 110°C.

原文???core.languages.en_GB???
文章編號9336666
頁(從 - 到)335-338
頁數4
期刊IEEE Electron Device Letters
42
發行號3
DOIs
出版狀態已出版 - 3月 2021

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