Flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation

Yeong Kang La, Liang Gee Chen, Tsung Han Tsai, Po Cheng Wu

研究成果: 會議貢獻類型會議論文同行評審

3 引文 斯高帕斯(Scopus)

摘要

This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

原文???core.languages.en_GB???
頁面144-147
頁數4
出版狀態已出版 - 1997
事件Proceedings of the 1997 International Conference on Image Processing. Part 2 (of 3) - Santa Barbara, CA, USA
持續時間: 26 10月 199729 10月 1997

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???event.eventtypes.event.conference???Proceedings of the 1997 International Conference on Image Processing. Part 2 (of 3)
城市Santa Barbara, CA, USA
期間26/10/9729/10/97

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