Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit

Yuh Kuang Tseng, Kuo Hsing Cheng, Chung Yu Wu

研究成果: 雜誌貢獻會議論文同行評審

摘要

This paper describes a new feedback-controlled enhanced-pull-down BiCMOS (FC-EPD-BiCMOS) logic scheme for the low-supply-voltage operation. Through the use of the feedback-controlled enhanced-pull-down structure, the driving capability is improved and bipolar transistor saturation during operation period is avoided. Based upon the proposed structure, both static and differential logic gates are developed. The new BiCMOS three-input NAND gate offers 35% reduction in the propagation delay time as compared to conventional BiCMOS circuits at 2.5 V supply voltage. The proposed three-input FC-EPD-BiCMOS CPL XOR/XNOR gate has 33% improvement in delay time as compared to conventional BiCMOS 3-input XOR/XNOR gates at 2.4 V supply voltage.

原文???core.languages.en_GB???
頁(從 - 到)23-26
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
出版狀態已出版 - 1994
事件Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
持續時間: 30 5月 19942 6月 1994

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