With the advent of VLSI technology, large collections of processing elements, which cooperate with each other to achieve high-speed computation, have become economically feasible. Since any functional error in a high performance system may seriously jeopardize the operation of the system and its data integrity, some level of fault tolerance must be incorporated in order to ensure that the results of long computations are valid. A concurrent error detection (CED) scheme is proposed for FFT networks which consist of (N/2)log//2 N 2-point butterfly modules. The method assumes that failures are confined to a single complex multiplier or adder or one input or output set of lines; such a model covers a broad class of faults. It is shown that only a small overhead ratio--O(2/log//2 N) of hardware--is required for the FFT networks to obtain fault-secure results. Finally, a time redundancy method is used to locate the faulty modules.