Fault-tolerant algorithms and architectures for real time signal processing

An encoding technique, the weighted checksum code (WCC), is proposed to achieve concurrent error detection in matrix arithmetic and signal processing on highly concurrent VLSI structures. In order not to increase the roundoff errors when the WCC is incorporated into the computation, a simple roundoff error analysis is used to guide the construction of the WCC. A data retry technique is then proposed to locate the faulty processors and identify the correct outputs. Such an approach provides rapid error detection with low hardware overhead while system performance is not significantly degraded for the sake of fault tolerance.