Fault modeling and testing of resistive nonvolatile-8T SRAMs

Yu Ting Li, Yong Xiao Chen, Jin Fu Li

研究成果: 書貢獻/報告類型會議論文篇章同行評審

3 引文 斯高帕斯(Scopus)


In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static power of a SOC is mainly constituted by the SRAMs. Resistive nonvolatile-8T (Rnv8T) SRAM has been proposed to alleviate static power and preserve data in power-down mode and provide fast poweron speed. A Rnv8T SRAM cell is composed of a 6T SRAM cell, two resistive devices, and two transistors. In this paper, we define several memristor-related faults for the Rnv8T SRAM considering electrical defects. Also, a March-like test algorithm which can cover simple SRAM faults and defined memristor-related faults are proposed. In comparison with the existing work, the proposed March-like test needs longer test time, but provides better fault coverage on the targeted faults.

主出版物標題Proceedings - 2016 IEEE 34th VLSI Test Symposium, VTS 2016
發行者IEEE Computer Society
出版狀態已出版 - 23 5月 2016
事件34th IEEE VLSI Test Symposium, VTS 2016 - Las Vegas, United States
持續時間: 25 4月 201627 4月 2016


名字Proceedings of the IEEE VLSI Test Symposium


???event.eventtypes.event.conference???34th IEEE VLSI Test Symposium, VTS 2016
國家/地區United States
城市Las Vegas


深入研究「Fault modeling and testing of resistive nonvolatile-8T SRAMs」主題。共同形成了獨特的指紋。