Fault modeling and testing of 1T1R memristor memories

Yong Xiao Chen, Jin Fu Li

研究成果: 書貢獻/報告類型會議論文篇章同行評審

55 引文 斯高帕斯(Scopus)


Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.

主出版物標題Proceedings - 2015 IEEE 33rd VLSI Test Symposium, VTS 2015
發行者IEEE Computer Society
出版狀態已出版 - 1 6月 2015
事件2015 33rd IEEE VLSI Test Symposium, VTS 2015 - Napa, United States
持續時間: 27 4月 201529 4月 2015


名字Proceedings of the IEEE VLSI Test Symposium


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國家/地區United States


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